1. Field of the Invention
The present invention generally relates to phase-locked loop. More specifically, some embodiments relate to a phase-locked loop system utilizing a combination of analog and digital components.
2. Related Technology
A phase-locked loop (PLL) is a control system that generates a signal having a fixed phase relationship to a reference signal. PLLs are widely used in radio, telecommunications, computers and other electronic applications. They may generate stable frequencies, recover a signal from a noisy communication channel, or distribute clock timing pulses in digital logic designs such as microprocessors.
A typical phase-locked loop (PLL) is shown in FIG. 1. The PLL 100 receives an analog reference signal 110 and compares it to a voltage-controlled oscillator (VCO) signal 122 fed from the output, generating a phase-error signal 112 as a measure of their phase difference. If the phase or the frequency of the reference signal (fR) does not equal the phase or the frequency of the VCO output (fVCO), the phase-error signal 112, after being processed by the charge pump 104, causes fVCO to deviate in the direction fIN, If conditions are right, the VCO 108 will quickly lock to fIN, maintaining a fixed phase relationship with the reference signal 110. To increase the instantaneous response of the system, the phase-error signal 112 is run through a high bandwidth direct update circuit 120 with a constant gain and combined with the charge pump output 114.
The charge pump circuitry 104 is typically implemented as a single pole integrator. Combined with the parallel direct update path, the PLL 100 creates a two-pole linear feedback loop and has a potential to cause system instability due to the nearly 180-degree phase margin of the system. Furthermore, due to the imperfect components in the charge pump circuit 104, the integrator creates imbalances, causing errors in the VCO output. This can be problematic in 90 nm CMOS circuitries as typically implemented in modern VLSI applications.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced